This invention relates to programmable logic integrated circuit devices (“PLDs”), and more particularly to input/output (transceiver) circuitry on PLDs.
PLDs are typically designed to be general purpose devices. As such, a given PLD product can be employed by each of many different users to perform the particular tasks required by that user. Each user customizes (programs or configures) the PLD product to perform the tasks that user needs to have performed. The more users a PLD product can satisfy, the greater the potential market for that PLD product. Greater market volume tends to reduce unit cost for the PLD product. Of course, giving a PLD product too much capability tends to increase its size and complexity, which can put upward pressure on unit cost. It is therefore important to find low-cost ways to increase the flexibility of use of PLD products.
There are many different communication data protocols for which it may be desired to use a PLD. Some of these may require one or more transceiver channels on the PLD to be used individually. Others may require various numbers of transceiver channels on the PLD to be used together. For example, a communication protocol may require the PLD to transmit four high-speed serial data signals synchronously or substantially synchronously. Another protocol may require the PLD to transmit eight high-speed serial data signals synchronously or substantially synchronously. Typically a requirement for such synchronism means that all of the synchronized outputs need to be clocked by the same clock signal with no more than an acceptably small amount of skew between the output channels. (Skew is time delay between the otherwise synchronized outputs of two channels.) Transceiver clock distribution architectures are known that can efficiently synchronize up to eight channels. But there is now increasing interest in communication protocols that require synchronization of more than eight channels.